The present application relates to integrated circuit memory chips, and particularly to chips which include low-power SRAM cells.
Sheet Resistance and Clock Speed
The patterned thin-film layers which are used for conduction in integrated circuit devices will typically have a very significant distributed resistance and capacitance, which imposed a significant time constant on signals routed through such layers.
The RC time constant of the gate can be reduced by making metal contact to the gate in more places. This effectively reduces the "R" term in the time constant. However, each such contact consumes some gate area. Moreover, in single-level-metal processes, the requirements of making source contacts severely constrain the possible geometries for gate contacts.
Silicides and Conductive Nitrides
One general technique for improving the conductivity of silicon and polysilicon layers is to clad them with a metal silicide and/or a conductive nitride (usually TiN). Many different metal suicides have been proposed for use; among the most common are titanium, cobalt, tantalum, tungsten, nickel, and molybdenum silicide.
One particularly convenient way to provide silicides is to use a self-aligned process, in which a metal is deposited overall and heated to react it with exposed silicon. The unreacted metal can then be stripped off. Such process are known as "saliciding."
Salicidation is not without costs and risks. With shallow source/drain depths, salicidation may lead to increased leakage. The potential problems are reviewed, for example, in S. Wolf, II SILICON PROCESSING FOR THE VLSI ERA at 142-152 (1990). Thus silicidation is often avoided in high-density low-power memories.
Innovative Structures and Methods
The disclosed inventions provide an integrated circuit memory fabrication process and structure, in which salicidation is performed on the periphery (and optionally on the ground lines) of a memory chip, but not on the transistors of the memory cells. This avoids leakage in the array, while preserving maximal speed in the peripheral logic.
This is advantageously, but not necessarily, used in combination with the sidewall nitride process disclosed in the parent application, which provides a self-aligned zero-offset contact process.